Technical papers

optimize your AoN domain to reach low-power The specificity of numerous battery-powered applications (such as Wearables, IoT, Wireless communication…) is to spend most of their time in a sleep mode (> 99%). In many cases, the analysis of the energy consumed at the battery level in each power mode shows that the power consumption in […]

In the promising market of the Internet of Things (IoT), System-on-Chips (SoCs) are facing complexity challenges and stringent integration requirements. The architectural definition, component selection and their integration of the power management systems play a major role in the quest of device minimization and battery lifetime maximization. Capless voltage regulators are seen as the best

Internet of Things (IoT) applications are getting numerous, more power-stringent and smaller with every generation, requiring tighter control of power management and maximized function integration. This includes the integration within the same SoC of power-efficient voltage regulators and noise-sensitive modules (e.g. RF) that must be supplied with the appropriate level of noise immunity. This article

Audio electronic systems are facing major changes since the rising of ubiquitous devices using voice capabilities. Audio processing combined with high performance converters is becoming the critical contributor to deliver the greatest sound experience. This has led System-on-Chip (SoC) providers and Semiconductor IP suppliers to find the best compromise between cost, performance and flexibility. To

This paper presents a novel 5.5 V resilient Pulse-Triggered-Level-Shifter (PTLS) with enhanced toggling speed. This PTLS is a based on a cascoded High-Voltage (HV) level-shifters and only uses 3.3 V, near minimum size, CMOS transistors. This HV level-shifter generates both floating and a full-scale output signals and is able to operate under supplies from 2.6

Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use. Decreasing the supply voltage will

Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not been widely adopted by standard cell library providers because of the difficulties related to timing verifications: pulse width integrity and hold time closure.

With the development of more and more power-consuming mobile applications, the battery lifetime has become the biggest challenge of a low-power System-on-Chip (SoC). Success in designing a low-power SoC requires successive attention to five intertwined networks: the exchange network between functional blocks through data busses, the clock distribution network, possibly enabling clock gating and frequency

Voice-controlled devices will continue to gain new market segments in the electronics industry in the coming years because voice technologies open new horizons for the user experience. The aim of this article is to help IP procurement managers, SoC architects and system makers using voice detection IP in their systems to assess and compare the

Current consumption of an IR-UWB receiver is reduced thanks to duty-cycling techniques applied to the full analog chain, thus benefiting from the impulsive nature of the signal. The coherent architecture performs down conversion by mixing the incoming pulse with a locally generated 2.75ns pulse template and needs only a 1GHz frequency synthesis instead of a