Technical papers

Abstract Covalidating hardware and software remains a complex task for SoC designers. Isolated Instruction Set Simulators (ISS) and hardware simulators are readily available from diverse suppliers, but none can offer a complete solution for simulating a whole SoC with its software application: i.e. simulation of the microprocessor together with interconnected peripherals: logic, analog, memories… which […]

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Abstract Modeling of complex electromechanical systems can be simplified by dividing the mechanical part of the system into basic physical effects. These basic physical effects have been used for microsystem modeling and – as shown in this paper – can also be used in modeling electro-mechanics of macro scale. The reuse of these models from

Abstract With the increase in the complexity of systems with mixed-signal components, many systems designers recognize advantages and necessity of the mixed-signal simulation of these systems as a whole. Unfortunately, modeling and simulating such complex systems takes an enormous amount of time. The first problem identified is the speed of analog simulation. The second problem

System-on-a-chip (SOC) designs involving mixed-signal virtual components (VCs) require integration with thousands of logic gates without noise interference. Meeting the challenges of this type of design, Dolphin Integration and NEC Electronics (Europe) recently created a Codec VC for audio and telecommunications applications. The design successfully integrated A/D and D/A converters, programmable- gain functions and digital

Abstract The paper features a methodology for the cooperative generation of micro-mechanical layouts and derivation of the respective circuit simulator models which is especially suited for systems requiring continuous mechanics even on system level. For these applications the final development level is lifted from layout to circuit abstraction which supports designers and boosts mechatronics intellectual

Semiconductor designers are now in the business of system design and significant productivity improvements can only be reached through an additional investment upstream in architectural understanding. Chip layout strategies shall now result from such upstream decisions implying new developments in: precharacterized cells used at the breadboard level, functional simulation using custom CAD tools. Applications of