SUCCESS for embedded soft and hard coverification of SoC
Embedded Systems, Israël, Tel Aviv
A.Magiorani, P.Sauge

Abstract

Covalidating hardware and software remains a complex task for SoC designers. Isolated Instruction Set Simulators (ISS) and hardware simulators are readily available from diverse suppliers, but none can offer a complete solution for simulating a whole SoC with its software application: i.e. simulation of the microprocessor together with interconnected peripherals: logic, analog, memories… which may be described in VERILOG-HDL, VHDL, SPICE, VHDL-AMS, C-language…

This article presents an innovative solution to fill the EDA gap between hardware and software designers allowing a sophisticated coverification between the application program of a microcontroller with its analog or logic peripherals.

It is based on a cosimulation methodology, SUCCESS™, using the debug capabilities of an Integrated Development Environment (IDE) combined with those of the mixed signal hardware simulator SMASH™.

The major benefit is not just to allow Virtual In-Circuit Emulation (ICE), i.e. the ICE debug capabilities with an electronic simulator at software level, but to provide the ICE capability at the beginning of the design flow, which drastically improve the Time-To-Market.

SUCCESS™ thus becomes the favorite solution to speed-up check-out at three stages of the SoC design flow: the choice of architecture, the SoC hardware configuration and the application program to embed in a SoC…

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