A unique mastering of the most advanced low power design techniques
A unique mastering of the most advanced low-power design techniques

- Near Threshold Voltage
- Adaptive Body Bias
- Power partitioning & DVFS enablement

Near Threshold Voltage

Every technology has an optimum energy point in terms of supply voltage called the minimum energy point (MEP).
MEP is usually slightly above or near the threshold voltage (NTV) of the technology. In order to leverage NTV, special libraries, compatible with low-supply voltages, are required.
We have created a unique range of NTV libraries allowing designers to enable ultra-low power consumption for the always ON domains of their SoCs.

Adaptive Body Bias

In the race for higher energy efficiency, digital designers face the impact of variations, which modify the actual chip specifications defined by the extreme variations cases (the so called “corners”). This tends to degrade significantly the energy efficiency of the chip. This is especially true at low-voltage, where temperature has a significant impact on chip performance.
To optimize the energy efficiency, SoC designers often use compensation techniques.

Through the control of transistor threshold voltage in FD-SOI technology, body bias acts as a fantastic control knob to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the Power-Performance-Area (PPA) trade-off up to 10x at low voltage.

We have been cooperating with GF over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop.

Adaptive Body Bias - ABB

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