In the race for higher energy efficiency, digital designers face the impact of variations, which modify the actual chip specifications defined by the extreme variations cases (the so called “corners”). This tends to degrade significantly the energy efficiency of the chip. This is especially true at low-voltage, where temperature has a significant impact on chip performance.
To optimize the energy efficiency, SoC designers often use compensation techniques.
Through the control of transistor threshold voltage in FD-SOI technology, body bias acts as a fantastic control knob to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the Power-Performance-Area (PPA) trade-off up to 10x at low voltage.
We have been cooperating with GF over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop.