Category: Technical papers

Improving loading time on advanced nodes with SMASH™ mixed-signal simulator
B. Dumas, C. Valla, F. Espalieu

In the latest advanced nodes, getting a quick loading time for large analog circuits becomes a decisive stake. This paper explains how the latest SMASH™ revision allows to reach it. SMASH™ is a seamless IC-PCB mixed-signal simulator enabling the development and verification of analog and mixed-signal Silicon IPs and Integrated Circuits (IC) as well as …

Improving loading time on advanced nodes with SMASH™ mixed-signal simulator
B. Dumas, C. Valla, F. Espalieu
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Improving battery-powered device operation time thanks to power efficient sleep mode
S. Genevey, C. Dominguez

Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall …

Improving battery-powered device operation time thanks to power efficient sleep mode
S. Genevey, C. Dominguez
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Standard cell libraries for Always-On Domain
D. Maurer

Standard-cell library offering is usually divided in three categories: 6/7-track library for cost driven requirements, 8/9-track library for mainstream requirements and 10/12-track library for high-speed requirements. Standard cell Libraries often includes Multi Vt / Multi-channel-length cells to provide further flexibility to achieve the best PPA trade-offs. However, the advent of battery-operated devices, which spend most …

Standard cell libraries for Always-On Domain
D. Maurer
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How to succeed a true low-power Always-On Domain?
FLIPPERS: News on standards for Systems-on-Chip

optimize your AoN domain to reach low-power The specificity of numerous battery-powered applications (such as Wearables, IoT, Wireless communication…) is to spend most of their time in a sleep mode (> 99%). In many cases, the analysis of the energy consumed at the battery level in each power mode shows that the power consumption in …

How to succeed a true low-power Always-On Domain?
FLIPPERS: News on standards for Systems-on-Chip
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Capless Regulators – Dealing with load transient
A. Lacourse

In the promising market of the Internet of Things (IoT), System-on-Chips (SoCs) are facing complexity challenges and stringent integration requirements. The architectural definition, component selection and their integration of the power management systems play a major role in the quest of device minimization and battery lifetime maximization. Capless voltage regulators are seen as the best …

Capless Regulators – Dealing with load transient
A. Lacourse
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Pairing Sensitive RF with Voltage Regulators for Noise-Free IoT Modules
A. Lacourse

Internet of Things (IoT) applications are getting numerous, more power-stringent and smaller with every generation, requiring tighter control of power management and maximized function integration. This includes the integration within the same SoC of power-efficient voltage regulators and noise-sensitive modules (e.g. RF) that must be supplied with the appropriate level of noise immunity. This article …

Pairing Sensitive RF with Voltage Regulators for Noise-Free IoT Modules
A. Lacourse
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PWM audio D/A converter: cost breaking while maintaining performances
P. Giletti & V. Richard

Audio electronic systems are facing major changes since the rising of ubiquitous devices using voice capabilities. Audio processing combined with high performance converters is becoming the critical contributor to deliver the greatest sound experience. This has led System-on-Chip (SoC) providers and Semiconductor IP suppliers to find the best compromise between cost, performance and flexibility. To …

PWM audio D/A converter: cost breaking while maintaining performances
P. Giletti & V. Richard
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A Novel High-Voltage 5.5 V Resilient, Floating and Full-Scale 3.3 V Pulse-Triggered Level-Shifter
Nicolas Laflamme-Mayer and Mathieu Renaud

This paper presents a novel 5.5 V resilient Pulse-Triggered-Level-Shifter (PTLS) with enhanced toggling speed. This PTLS is a based on a cascoded High-Voltage (HV) level-shifters and only uses 3.3 V, near minimum size, CMOS transistors. This HV level-shifter generates both floating and a full-scale output signals and is able to operate under supplies from 2.6 …

A Novel High-Voltage 5.5 V Resilient, Floating and Full-Scale 3.3 V Pulse-Triggered Level-Shifter
Nicolas Laflamme-Mayer and Mathieu Renaud
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Methodology to lower supply voltage of standard cell libraries
B. Arricca

Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use. Decreasing the supply voltage will …

Methodology to lower supply voltage of standard cell libraries
B. Arricca
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Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems
M. Louvat

Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not been widely adopted by standard cell library providers because of the difficulties related to timing verifications: pulse width integrity and hold time closure. …

Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems
M. Louvat
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