Standard-cell library offering is usually divided in three categories: 6/7-track library for cost driven requirements, 8/9-track library for mainstream requirements and 10/12-track library for high-speed requirements. Standard cell Libraries often includes Multi Vt / Multi-channel-length cells to provide further flexibility to achieve the best PPA trade-offs.
However, the advent of battery-operated devices, which spend most of their time in a sleep mode, translates into an emerging need for standard-cell libraries specifically optimized for addressing the challenge of always-on power domain. Indeed, the always-on domain, typically including a logic block that remains active in all operating modes, must satisfy specific requirements in terms of operating voltage range and power consumption targets that may not be efficiently addressed by a conventional standard cell library.
The comparative analysis of the contents of three always-on power domains, as typically seen with SoCs targeting Wearables applications, enables to identify the characteristics of the standard-cell library required to reach the targeted key performance indicators.
This technical paper illustrates, with concrete examples based on 55 nm uLP-eFlash process, the various choices which may guide the SoC designer to select the most suitable standard-cell library for implementing the always-on logic among:
- Conventional high-density logic library, operating at core transistor voltage (such as SESAME uHD or HD library).
- Logic library operating at ultra-low voltage (such as SESAME NTV library).
- Logic library with extended operating voltage range (such as SESAME BiV library)
This article concludes with recommendations for selecting consistently the other silicon IPs needed for designing the always-on domain.
To go further, discover our libraries for Always-on domains.