The ultra-low power targets of a battery-powered SoC – be it for IoT, Wearables, Wireless audio, BLE, SmartHome, Sensor hubs, Wireless automotive, MCUs… – now benefit from the widest panoply of low-power and dense memories proven to safely operate down to 0.81 V and to retain data down to 0.6 V.
Granting up to 70% power consumption savings compared to conventional memory generators at 55 nm LP, the following set of memory generators has successfully passed all stages of TSMC9000 silicon qualification, both in 55 nm uLP and 55 nm uLP eFlash:
- Single-port RAM, SpRAM RHEA
- 1-port Register File, 1PRF AURA
- 2-port Register File, 2PRF ERA
- Dual-port RAM, DpRAM ERA
- Late programmable via ROM, sROMet TITAN
SoC designers have the flexibility to get the best performance trade-off, between speed and low-power, by selecting any operation voltage between 1.2 V and 0.9 V thanks to off-the-shelf available characterizations at 1.2 V +/- 10%, 1.1 V +/- 10%, 1.0 V +/- 10% and 0.9 V+/- 10% as well as additional user-specific characterization corners.
As facing the increasing architectural complexity of SoCs to lower their power consumption is challenging, Dolphin Integration streamlines SoC integration by proposing its RAMs with multiple power supply schemes – single rail, dual active rails, dual retention rails – with and without embedded power switches.
Most of the memory generators are provided in the frame of the TSMC sponsorship program, i.e. free of license fee. Register right away on MyDolphin private space to assess the achievable savings for your coming SoC using our on-line memory generators.
Request further information on these memories, and on the complete and consistent set of silicon IPs for TSMC 55 nm uLP / uLP-eFlash.
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Meet us at the TSMC symposiums in Santa-Clara (USA) on March 15th and in Shanghai (China) on March 28th.