This paper presents a novel 5.5 V resilient Pulse-Triggered-Level-Shifter (PTLS) with enhanced toggling speed. This PTLS is a based on a cascoded High-Voltage (HV) level-shifters and only uses 3.3 V, near minimum size, CMOS transistors. This HV level-shifter generates both floating and a full-scale output signals and is able to operate under supplies from 2.6 V (down to 1.8 V with strategic contextual gate control on cascode and protection transistors) up to 5.5 V, without endangering any transistors. This PTLS can drive pMOS logic, nMOS logic or 5.5 V I/Os simultaneously with loads up to 250 fF on every output nodes (1.25 pF total), using only one buffering stage. The proposed circuit was extensively validated by simulations for every technological corners, temperatures from -40 °C up to 125 °C, operating voltages and output capacitances, so that this HV level-shifter is reliable under any operating conditions. The simulated circuit shows a 2 39 ns maximum delay under typical conditions and a worst case of 10.4 ns. The circuit draws no static power and shows a typical dynamic power consumption of 25.92 µW/MHz with maximum operating frequency of 261.8 MHz.
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