How to succeed a true low-power Always-On Domain?
FLIPPERS: News on standards for Systems-on-Chip

optimize your AoN domain to reach low-power

The specificity of numerous battery-powered applications (such as Wearables, IoT, Wireless communication…) is to spend most of their time in a sleep mode (> 99%). In many cases, the analysis of the energy consumed at the battery level in each power mode shows that the power consumption in active modes is a second order contributor to the energy consumed over time.

As a result, minimizing the current drawn in sleep mode(s), during which only a subset of the SoC remains powered, is critical for allowing products to run for years rather than months without battery recharge or replacement. This domain of the SoC, which is supplied in all power modes, forms the “Always-On power domain” (a.k.a AON power domain).

The Always-On Domain embeds the means to start-up the SoC and to wake it up from “sleep” modes. It typically includes the logic to control the start-up of the SoC, as well as to control the transitions between SoC modes, e.g. turning on/off power domains and their associated clocks and supplies. It also embeds the always-on triggers which monitor the events used to wake-up the SoC, along with the elements related to SoC infrastructure (power supply, clock, I/O…).

Our complete offering of silicon IPs dedicated to always-on power domains encompasses Foundation IPs, Feature IPs as well as Fabric IPs to satisfy the requirements of each SoC. Furthermore, the diversity of our offering – e.g. standard-cell libraries either designed with thick oxide transistors (BIV) or designed to operate near the threshold voltage (NTV) – provides the capability to reach the power consumption targets of a specific SoC in a selected fabrication process.

Three contexts representative of a wide range of low-power SoCs are presented to enable appreciating the performance savings achievable with Dolphin Integration’s offering, be it for ensuring the longest sleep without battery recharge/change or for minimizing silicon area and BoM costs.
Such a comparative analysis shows, for instance, that a thick oxide library may not be the best solution to achieve the lowest power consumption in sleep mode specifically when the power consumption is dominated by the leakage of a RAM in retention mode…

Discover the performance savings achievable for your SoC