News releases

The industry’s focus on battery-powered devices sets new expectations in terms of energy saving for a wide range of applications such as IoT, wearables and wireless MCUs. Meeting the underlying low-power challenge requires a new class of silicon IPs to enable unmatched power consumption figures and new IoT SoC architectures leveraging operating modes with reduced […]

In our connected and mobile world, IC designers are striving to save µA or even nA of power consumption to extend battery usage without recharge. IoT applications bring the need for LP to new heights involving the adoption of more complex SoC architectures based on multiple power domains, which also require embedding the whole power

Low-power SoCs rely on two design techniques, namely multiple operating frequencies and supply voltages to minimize dynamic power and coarse grain power gating by shutting down parts in sleep mode to save a large amount of leakage power (e.g. up to 99% saving). The implementation of such design techniques requires the insertion of specific cells

Launching any SoC on a highly competitive market demands a differentiation for which Hisense was searching for an ultra low-power solution to extend battery life-time of wireless-connected devices. Designing such an integrated circuit introduces new challenges: silicon area, power consumption and BoM cost must be aggressively reduced, while dealing with noise issues in a mixed-signal

For RFID Tags, dynamic power is a critical factor as the capability for lower power translates immediately into a wider range of detection (RFID tag read range) and/or a highest identification rate in the same range. The main degree of freedom to improve power and area of RFID tag is located in the digital block.

The trend for intuitive and simple user interfaces is driving the growing demand for voice control, either for complementing or for replacing keyboards, touchscreens and other traditional controls. This need for a new generation of green microphones leads to embedding the capability for waking up the rest of the system as soon as a voice

For integrated circuits with really high volumes, such as MCUs, SESAME uHD (ultra High Density), the flagship product in Dolphin Integration’s standard cell library offering, is paramount to decrease die costs. It stars its patented pulsed latches as « Spinner Cells » instead of standard D-flip flops, openly documented in “Thorough validation: the conundrum of Pulsed latch

Leading-edge More-Than-Moore process variants at 55 nm for the challenges of IoT and wearable devices deserve equally state-of-the-art low power design methodologies: it involves Silicon IPs for embedding the Power Regulation Network and for the SoC Mode Control Network, together with the transfer of know-how to ensure a safe and smooth design-in. Designers of low-power

Minimizing the PCB footprint and the BoM cost implies embedding the Power Regulation Network (PRNet) in the SoC. Meanwhile, minimizing drastically the SoC power consumption involves implementing several modes of activity to turn on and off different functions of the SoC, which generates noise on the supply lines during mode switching.   Dolphin Integration is

SoC designers are at ease to compare the performances of memories. It indeed only requires selecting some memory capacities and checking that performances are provided in the same conditions among the suppliers. Area, speed (access time), power consumption in dynamic mode and leakage may be then objectively compared. What about Standard Cell libraries? Not an