In our connected and mobile world, IC designers are striving to save µA or even nA of power consumption to extend battery usage without recharge. IoT applications bring the need for LP to new heights involving the adoption of more complex SoC architectures based on multiple power domains, which also require embedding the whole power regulation network.
Such advanced SoC architectures significantly increase design complexity and may thus severely impact Time-to-Market and costs. As the power domains are dynamically switched on and off, the selection of the SoC architecture must be performed in full awareness of noise issues.
This webinar unveils a step-by-step design methodology to specify the power budget and master the design of ultra low-power and mixed signal SoCs, based on a concrete example.
By attending this webinar, architects and designers will discover that the combination of this design methodology with the use of SoC Fabric IPs, for building the clock, power and control networks, partakes in ensuring:
- the best TTM with the lowest risks,
- the optimization of SoC performances with the best trade-off between area, BoM cost, and power consumption.
This webinar is for SoC architects and designers targeting to decrease their SoC power consumption, as well as project leaders and design methodology managers needing to deploy a low-power design flow for safer and faster tape-outs.
It provides insights into low-power architecture selection along with tricks & tips for ultra low-power SoC implementation.
Dolphin Integration has proven the effectiveness of this structured design methodology ensuring IP compatibility with its Taishan demochip designed in partnership with TSMC at 55 nm uLP eF.
select your time schedule: November 15, 9:00 AM PST or November 22, 10:00 AM GMT
For more information, contact Aurélie Descombes, Marketing Manager