Oct 31, 2016

Minimize power domain leakage and design margins while shortening Time-To-Market

Low-power SoCs rely on two design techniques, namely multiple operating frequencies and supply voltages to minimize dynamic power and coarse grain power gating by shutting down parts in sleep mode to save a large amount of leakage power (e.g. up to 99% saving).

The implementation of such design techniques requires the insertion of specific cells (power switch cells, isolation cells, level shifters…) at the appropriate places and in the appropriate manner for the design to achieve its minimum power with the highest reliability. Indeed, further power savings come at the expense of implementation complexity and thus of higher risk of malfunction.

CLICK, an SoC Fabric IP from Dolphin Integration, is a universal power gating solution which enables designers to easily and safely implement power gating. Promoting a ring-style implementation, CLICK is a library-independent solution which solves by construction the design issues left up to the designer with traditional solutions (PMK, POK…). CLICK is applicable to any power domain requiring power gating whatever its nature, whether a logic block or hard macro.

With its patented cell, the Transition Ramp Controller (TRC), CLICK automatically limits the inrush current, controls the resulting IR-drop and optimizes the wake-up time of the power domain. Thanks to the register programmability of the TRC, the maximum inrush current allowed at wake-up time can be easily tuned, even after tape-out (!), whereas traditional daisy chains provide neither the same flexibility nor the safety of a control scheme.

Voltage drop at regulator output for different TRC settings – TAISHAN project


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Finally, CLICK is fully compatible with the DELTA voltage regulator library and its MAESTRO embedded control network for the design and implementation of low-power SoCs.

Note: CLICK is fully compatible with both Cadence and Synopsys Place and Route solutions.

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