Category: News releases

Leading-edge More-Than-Moore process variants at 55 nm for the challenges of IoT and wearable devices deserve equally state-of-the-art low power design methodologies: it involves Silicon IPs for embedding the Power Regulation Network and for the SoC Mode Control Network, together with the transfer of know-how to ensure a safe and smooth design-in. Designers of low-power …

Do not miss the Green Thursday offering for ultra Low-Power SoCs at 55 nm… Read More »

Minimizing the PCB footprint and the BoM cost implies embedding the Power Regulation Network (PRNet) in the SoC. Meanwhile, minimizing drastically the SoC power consumption involves implementing several modes of activity to turn on and off different functions of the SoC, which generates noise on the supply lines during mode switching.   Dolphin Integration is …

Pushing SoC optimization to the next level with all risks managed Read More »

SoC designers are at ease to compare the performances of memories. It indeed only requires selecting some memory capacities and checking that performances are provided in the same conditions among the suppliers. Area, speed (access time), power consumption in dynamic mode and leakage may be then objectively compared. What about Standard Cell libraries? Not an …

Try and adopt Motu-Uta, the benchmark for a fair evaluation of Standard Cell libraries Read More »

As an unavoidable technology for IoT, the Bluetooth Low Energy (BLE) protocol is designed to enable very low-power consumption devices. To save power, designers of BLE ICs need to implement a wake-up system, sufficiently accurate from a time tracking point-of-view, to ensure that paired devices operate in the same time-window. The higher the clock drift, …

Low-power of Bluetooth SoCs depends on our low frequency oscillators Read More »

Intuitive and simple user interface drives the growing demand for voice control, either complementing or replacing keyboards, touchscreens and other traditional controls. The multiplicity of solutions available for Voice Activity Detection (VAD), combined with the absence of vendor-independent benchmarks, makes it hard for any purchaser to select the best solution. Today, neither unified performances nor …

Try and adopt MIWOK™, THE benchmark for Voice Activity Detectors (VAD) Read More »

The optimization of a Power Management Network (PMNet): it is no longer about PMIC or embedded PMU efficiency on Watts, but now, about the waste of energy for the whole SoC in mW for IoT. IoT is all about wireless communication, which demands dealing with two major noise issues: the ripple loop with the HF-RF, …

The DELTA standard for voltage regulators breaks the habits for 40 nm IoT SoCs Read More »

Expectations of long battery life for ever more feature-packed applications require ultra low-power optimization to reduce overall power consumption. Reaching the low-power consumption target for your SoC implies: To turn on/off different functions through clock gating and power-gating techniques for implementing power domains To manage the transitions between modes of these power domains This previously …

Easy and secure solution to manage SoC power mode transitions Read More »

Portable devices, like Wearables or Smart devices, spend most of their time (> 98%) in deep-sleep/Hibernate mode. It thus is crucial to minimize the energy drawn by the always-operating functions, i.e. the always-on domain, in order to extend battery lifetime. Indeed, even if the always-on logic represents usually a small part of the SoC, its …

Optimize the power of always-on logic with SESAME NTV library in TSMC 55 uLP / uLP-eF process Read More »