New Dual Port memory compilers in TSMC 40 nm

May 21, 2018

New Dual Port memory compilers in TSMC 40 nm

Dolphin Integration, leader in innovative design solutions for the next generation of energy-efficient System-on-Chips, has announced the launch of its new Dual Port RAM compiler ”ERA” in TSMC 40 nm. This cost-effective RAM compiler creates memories maximizing battery life whilst reducing silicon area. Capable of generating instances ranging from 64 bits to 288 kbits, it also features a new ultra-low leakage stand-by “NAP” mode, allowing a leakage reduction of up to 35% compared to standard stand-by modes with a single clock cycle wake-up time. WIPE, a new feature available as an add-on, allows the reset of the memory in only 5 clock cycles.

The ERA Dual-Port memory compiler is available in Single or Dual Rail with high density, low power, low leakage optimization, in TSMC 40 nm uLP or uLPeF. Power switches can be embedded as an option.

The ERA memory compilers are available for evaluation on your private ”MyDolphin” portal.

The ERA architecture has already been silicon proven in TSMC 55 nm and migrated to the TSMC 40 nm technology node. The following views are available:

  • Simulation (Verilog)
  • layout (GDSII)
  • footprint (LEF)
  • timing/power (Liberty)
  • MBIST (Tessent) models

Access to the evaluation of the ERA Dual-Port memory compiler in TSMC 40 nm

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