Conference papers

Guidelines for Verilog-A Compact Model Coding MOS-AK 2009, Sept. 18 2009 in Athens Gilles DEPEYROT & Frédéric POULLET Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and IEEE 1364.1-2002), […]

Need for A standard subset of Verilog-A for Compact Modeling MOS-AK 2009, 2-3 April 2009 at IHP in Frankfurt /Oder Gilles DEPEYROT & Frédéric POULLET Without any doubt, Verilog-A is now a standard language for compact modeling. But, much like for synthesis, a standardization of a subset of Verilog-A, along with a definition of good

Micro-Electro-Mechanical Systems (MEMS) as inertial sensors, like accelerometers and gyroscopes, are finally becoming attractive for many industrial applications, and their potential range of use is about to explode in the coming years. The application trend towards high resolution, reliability, and miniaturization, pushes system integrators to combine both the inertial sensor and its application-specific integrated circuit

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You will Find this article on the IEEE website

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Abstract The opportunities to integrate more and more functionality into a (micro)system-in-a-package (SiP) heavily call for advanced methodologies in modeling and simulation for complete systems. For a microelectronics company like Infineon Technologies, the top-level simulation of our products, i.e. the above microsystems, is not a nice-to-have feature – it is a must! Iterating on the

A new paradigm is evolving because a SoC is not a mere Microcontroller IC just fashionably renamed, but a Programmable Architecture with hierarchical design-in of Virtual Components of Silicon IP. All portable consumer SoC’s tend to become mixed signal for cost-effectively embedding Power Management Units or DC-DC converters as well as A/D and D/A converters.

Abstract Systems-on-Chip integrators are facing the need to integrate the mixed signal virtual components, which best perform sensitive I/O functions. They must address hierarchically the interactions, instead of the traditional approach operating flatly on the lowest level, as this suffers from a double- whammy, as follows. A new integration process must make room for the