IDRT-aware SoC Integration Flow
IP/SOC 2005
A.Bonzo, L.Engels, F.Poullet

Abstract

Systems-on-Chip integrators are facing the need to integrate the mixed signal virtual components, which best perform sensitive I/O functions. They must address hierarchically the interactions, instead of the traditional approach operating flatly on the lowest level, as this suffers from a double- whammy, as follows.

A new integration process must make room for the innovative concepts of subdivision into power- supply islet but also for the quantification of the “Injected Disturbance Rejection Threshold” (IDRT) of noise sensitive virtual components.

We thus present a novel approach to mixed signal SoC Integration, namely a hierarchical IDRT-aware SoC design flow.

The dual key points in such a design flow are on the one hand floor-planning with islet definitions for level-shifting and macrocell placement, and on the other hand assessments of resilience to disturbances in view of disturbance sources in the Rest-of-SoC. Ultimately, Virtual Sockets as promoted by VSIA enable hierarchical verifications through simplified representations of hard components at appropriate levels: DRC, LVS, ERC, STA, and more…

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