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Presentation: Simplify Energy Efficient designs with cost-effective SoC Platform TSMC Open Innovation Platform – Ecosystem Forum Santa Clara, Beijing, Israel

Speaker: Pierre Gazull, Business Development Manager Many market and industry analysis report that due to the slowdown of Moore’s law, improvement in Energy Efficiency for the next generation designs should be sought out with chip customization and AI capabilities. These innovative features will help SoC designers to overcome the fact that technology scaling is not […]

Presentation: Simplify Energy Efficient designs with cost-effective SoC Platform TSMC Open Innovation Platform – Ecosystem Forum Santa Clara, Beijing, Israel Read More »

Presentation: Power management solution to enable the fastest and safest design of Energy Efficient SoCs – Samsung Partner Forum 2019, San Jose.

Speaker: Frederic Renoux, EVP of sales Achieving the best energy efficiency have evolved from an objective of most advanced SoCs targeting battery-operated devices to become a key constraint of most applications, be it consumer, automotive and even servers. Improved energy efficiency can indeed translate into longer operation without battery replacement or recharge as well as

Presentation: Power management solution to enable the fastest and safest design of Energy Efficient SoCs – Samsung Partner Forum 2019, San Jose. Read More »

Tutorial : Dynamic aging compensation – the next key enabler of automotive products
IRPS 2019

Speaker: Vincent Huard, CTO Vincent Huard presented this tutorial together with Joerg Winkler, from GLOBALFOUNDRIES during the tutorial session at IPRS conference (International Reliability Physics Symposium). The automotive products, driven by ADAS needs, are now moving to very advanced CMOS nodes. This trend is helping a lot from soft errors perspective with a reduced architectural

Tutorial : Dynamic aging compensation – the next key enabler of automotive products
IRPS 2019
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Unlocking the full potential of Body Biasing with FD-SOI to design the most Energy Efficient SoC
IP SoC Grenoble

Speaker: Frederic Renoux – EVP Sales Frederic Renoux introduced this presentation during Low Power challenge session at the IP SoC Grenoble on december 06, 2018. To discover our innovative offering addressing the Energy Efficiency Challenges, contact us Download this press release

Unlocking the full potential of Body Biasing with FD-SOI to design the most Energy Efficient SoC
IP SoC Grenoble
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Addressing the Energy Efficiency Challenges of IoT end points
Japan SOI Design Workshop

Dolphin Integration introduced this conference paper at the Japan SOI Design Workshop on october 25, 2018. During this workshop, we have met leading companies working with SOI technologies and discussed about the challenges addressed when designing with FD & RF SOI technologies. To discover our innovative offering addressing the Energy Efficiency Challenges, contact us Access

Addressing the Energy Efficiency Challenges of IoT end points
Japan SOI Design Workshop
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Addressing the Energy Efficiency Challenges of IoT end points
SOI Consortium Shanghai

Speaker: Frederic Renoux, eVP of Dolphin Integration Improving the energy-efficiency of SoCs has become a major challenge for most applications, be they battery-powered such as Wearables or Automotive or line-powered such as Home Multimedia or Servers. The integration of the power regulation network on SoC is the best approach to improve energy-efficiency while reducing BoM

Addressing the Energy Efficiency Challenges of IoT end points
SOI Consortium Shanghai
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Cost-effective design of next generation of ultra-low power SoCs – More Intelligent Design needed
D&R IP-SoC 2017

The semiconductor industry is entering into the new era of More Intelligent Designs, whereby more complex SoC power architectures must be adopted to meet the low power challenges of battery-powered devices, as leveraging the fabrication process capabilities is no longer sufficient. Dolphin Integration’s “Enabling Trio”, combining new a breed of silicon IPs, EDA solution and

Cost-effective design of next generation of ultra-low power SoCs – More Intelligent Design needed
D&R IP-SoC 2017
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Concerned about security? Don’t leave your memories unprotected
D&R IP-SoC 2017

Today’s typical SoC includes between tens to hundreds of embedded SRAM instances & Register-Files, used in practically every aspect of the system, and storing data of various levels of importance – from worthless statistical data & media to priceless information such as personal data, passwords and security keys. Leaving memory blocks unprotected is making them

Concerned about security? Don’t leave your memories unprotected
D&R IP-SoC 2017
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