Speaker: Frederic Renoux, EVP of sales
Achieving the best energy efficiency have evolved from an objective of most advanced SoCs targeting battery-operated devices to become a key constraint of most applications, be it consumer, automotive and even servers. Improved energy efficiency can indeed translate into longer operation without battery replacement or recharge as well as into better performances and reliability for high-performances SoCs constrained by power dissipation. This presentation starts with an overview of key power management design techniques, such as power domain partitioning, DVFS and body biasing which is more specific to FDSOI processes. While such techniques are known in our industry, implementing them is currently a major burden as it involves specific design know-how, more design efforts and new risks. SPEE PM is an innovative power management design platform for logic-based design flows. It encompasses a consistent and complete set of optimized power management IPs with dedicated utilities to design much faster and safely an SoC, whatever its complexity. A concrete example illustrates how a fabless company can leverage SPEED PM to meet on-time and cost-effectively the energy-efficiency targets.