Smart electric meters are fundamental to the successful deployment of smart grid technology, as they improve grid reliability and user consumption control and reduce electricity
theft. The variety of consumers’ emerging needs requires a much wider offering of energy metering systems-on-chip (SOCs), paving the way for more fabless companies to enter the energy measurement field. Energy meter-specific analog front-end (AFE) devices, which combine high performance with cost reduction, are thus needed to complement standard IC offerings.
Today’s energy metering standards demand higher accuracy and lower power consumption which, in turn, challenges system designers to deliver more competitive AFEs. This article reviews those challenges and presents a solution based on a multiplexed channel architecture that delivers ultra-high resolution, along with very low-power consumption and silicon area. First, the article gives an introduction to smart electric meters and their specifications. Second, it presents the architecture used in conventional energy meter AFEs, and compares the trade-offs of using a high-performance analog-to-digital converter (ADC) versus using a lower performance ADC together with a programmable gain amplifier (PGA). Third, a new multiplexed AFE architecture for three-phase energy meters, which yields considerable area and power savings while simplifying the integration of application-specific ICs (ASICs), is detailed. Finally, the need for multi-domain simulation to guarantee AFE performances at the system level is discussed…
