To reduce the Bill-of-Material (BoM) and to simplify their usage, System-on-Chips (SoC) become more and more complex due to the integration of a large number of features previously located on board. This increase of complexity, combined with economic and green stakes leads to draw new optimizations, such as partitioning the SoC in different subsets with power and voltage islets supporting several states of activity. Theses states allow minimizing power consumption for islets that are not used or are operating with reduced speed performances.
Embedding the Power Management Network (PMNet) enables a second pass of optimization towards reduction of BoM and power consumption. One of the main challenges for SoC Integrators is then to properly select the PMNet – including power regulators, external and internal capacitors – to sustain the voltage drops caused by SoC activity changes (transition when islets are waken up …), but also to take critical decisions on the integration and the package assembly.
A new generation of power kit library is required, to ease the PMNet deployment and its reuse in successive circuits, to improve the Time-To-Market and to secure the PMNet integration into SoC.