Webinar: Recipe to consume less than 0.5 µA in sleep mode

Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain” (a.k.a AON power domain) is pivotal.

To meet customer expectations, ensuring a current consumption of the Always-On power domain – incl. blocks in retention mode – not higher than 500 nA is pivotal. To reach this target, the power network architecture needs to be carefully considered.

After the success of our webinar presenting the recipe for a low-power SoC, our chef is back with a successful and proven recipe – in Taishan demochip at TSMC at 55 nm uLP eF – to ensure the lowest power consumption in sleep mode(s).

To watch this webinar, please register to our customer private space, MyDolphin >

Webinar agenda

First, we will accord on the definition of what an always-on power domain is and on the different modes of a low-power SoC.
Then, we will illustrate why minimizing the power consumption of the Always-on Domain is crucial for the competitiveness of an uLP SoC which spends most of its time in sleep mode.

A comparative analysis between five power architectures to implement the always-on power domains, will enable to identify the characteristics of silicon IPs required to reach the targeted performance optimization, be it minimal the smallest silicon area, the lowest BoM cost or the lowest power consumption.
This webinar illustrates, with concrete examples based on 55 nm uLP-eFlash process, the various choices which may guide the SoC designer to select the most suitable set of silicon IPs (incl. standard-cell libraries) for implementing the always-on logic.

The objective comparison, through a figure of merit, will help select the most appropriate power architecture to meet your SoC requirements.

Who should attend?

SoC architects and designers targeting to decrease their SoC power consumption, as well as project leaders and design methodology managers needing to deploy a low-power design flow for safer and faster tape-outs.
Pre-requisite: it is better to have notions on low-power architectures incl. on power domains. If you need, you can request an access to the record of our first webinar dealing on this subject “The proven recipe of an LP SoC”.


To watch this webinar, please register to our customer private space, MyDolphin >