Launching any low-power SoC on a highly competitive market requires true differentiating factors. For IoT applications requiring ultra low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimize power modes by partitioning the SoC. This minimizes dynamic power in active modes, as well as power leakage in stand-by modes. Dolphin Integration is on a continuous quest to provide new solutions to their customers, to help them address their challenges.
Dolphin Integration announces the availability of the Calypso architecture. Calypso is a SpRAM optimized for low-power SoCs in TSMC 28 nm HPM technology.
This Single-port SRAM is designed to optimize power consumption, with gains between 20 and 30% compared to alternative solutions in 28 nm.
Detail from a corner of Calypso SpRAM 28
The SpRAM Calypso reaches such a performance thanks to its data retention mode, with a memory core lowered to 0.63 V. This minimum voltage retention feature allows leakage to be divided by between 2 and 10 (depending on memory size) compared to other memory compilers in stand-by mode.
SpRAM Calypso is part of a our 28 nm HPM portfolio, which includes:
- ultra high-density 6-track standard cell libraries,
- our unique cache controller, R-Stratus-LP, both improving speed and reducing power consumption by up to 3 times, compared to stand-alone eFlash memory,
- our innovative MAESTRO™, a fabric IP making the implementation of the Activity Control Unit of a low-power SoC easy and safe.
Visit our memory section to get further information on our offering