The DELTA standard for voltage regulators breaks the habits for 40 nm IoT SoCs

Feb 22, 2016

The DELTA standard for voltage regulators breaks the habits for 40 nm IoT SoCs

The optimization of a Power Management Network (PMNet): it is no longer about PMIC or embedded PMU efficiency on Watts, but now, about the waste of energy for the whole SoC in mW for IoT.

IoT is all about wireless communication, which demands dealing with two major noise issues:

  • the ripple loop with the HF-RF, disturbed by the inner frequency of the switching regulator (DC-DC)
  • the noise propagation from the logic blocks, such as application processors, at diverse frequencies aggravated by DVFS

Making the right choices for embedding PMNets into System-on-Chips (SoC) is thus challenging and might result in contradictions for the integrator.

To satisfy the growing number of ultra low-power SoCs targeting 40 nm, Dolphin Integration now provides its Reduced Power Kit Library, fully compliant with the DELTA standard, to facilitate, optimize and secure the implementation of the Power Management Network.

The Reduced Power Kit Library (RPKL) at 40 nm encompasses a « kernel » of voltage regulators to cover most SoC requirements: high-efficiency switching regulator, low noise linear regulator, ultra-low quiescent linear regulator…
Per the DELTA rules, each type of voltage regulator is spanning the standardized Interfaces for Distribution of Power (IDP) to support any kind of conventional input voltage of a SoC (from 1.8 V up to 5.5 V USB), and to supply loads from 3.3 V down to 0.55 V with a maximum current up to 500 mA.

  •  eSR-Niagara: this switching regulator provides the best compromise between  power savings (down to a mere 5 % of energy wasted) and small silicon area.

A safe pairing with HF-RF loads is feasible thanks to the characterization of the ripple and of the noise transfer functions of the eSR.

  • qLR-Aubrey: this ultra-low quiescent current Linear Regulator, with an Iq of 150 nA including the voltage reference, is ideal to supply loads up to a total of 1 mA, as embedded in the Always-on Power Domain.
  • nLR-Charny: this ultra low noise linear regulator supplies sensitive Analog converters or RF loads, with a PSSR as low as – 70 dB at 10 kHz, and with 50 μVRMS total integrated noise in the whole bandwidth.
  • iLR-Victoria: this linear regulator is best for downstream regulation of logic loads or conventional analog loads. It combines small area with fast load transient and a fast wake-up time.
  • Retention Alternative Regulator (RAR): This regulator is ideal to support power islands of a SoC with the lowest waste of energy in each power mode: active and retention down to 0.55 V.

To be progressively enriched.

The compliance with the Delta Standard is essential to implement the PMNet of any SoC for:

  • Providing designers with proven voltage regulators
  • Securing the integration by ensuring the correct matching of the regulators and their loads thanks to relevant specifications and advanced views
  • Avoiding iterative design loops by defining a fair distribution between regulator accuracy, IR-drop and load/line transient effects

Contact us and get more information on our Low power Silicon IP panoply at 40 nm


To go further in the low-power SoC optimization, Dolphin Integration provides all the Foundation and Feature IPs to implement a diversity of power domains:

  • Logic power domains with libraries of memories and standard cells, low power microcontrollers and cache controller.
  • Analog power domains with audio converters.
  • Always-on power domains with ultra low power standard cells, low power oscillators and wake-up triggers.

Together with the Fabric IP named Maestro for the fast implementation of the control network in order to safely turn on and off the power domains of the SoC.

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