Expectations of long battery life for ever more feature-packed applications require ultra low-power optimization to reduce overall power consumption.
Reaching the low-power consumption target for your SoC implies:
- To turn on/off different functions through clock gating and power-gating techniques for implementing power domains
- To manage the transitions between modes of these power domains
This previously complex task for SoC integrators is made straightforward thanks to Maestro™: a fast, easy and secure solution enabling the design of the Activity Control Unit (ACU) or Power Management Unit (PMU Logic). It serves to manage power island modes and mode transitions whatever the complexity of the SoC.
Discover the unique Maestro™ network
The Maestro™ network relies on different principles:
Smart combination of soft and hard modules which structure and simplify the hierarchical design of the ACU or PMU Logic
- More flexible and reusable than a “hand-made” interconnection and faster development than a full C/C++ solution
- Application of the principle of subsidiarity which eliminates the risk of “conflict of modes” between shared power regulators and clock generators
A dedicated control bus
- Independent from the functional busses, thus authorizing the construction of the power island architecture over the functional block architecture
Save design time – Secure design implementation
Keep flexibility – High reliability – Reduce power consumption
In addition to Maestro™, discover how to assemble and optimize your power management network thanks to the DELTA standard.
