With the growth of markets related to the Internet of Things, the requirements in terms of very low-power consumption for the connected “things” push SoC/ASIC designers and architects to hunt down mA, and even µA, from specification until first silicon prototype validation.
The level of experience in low-power strategy definition and implementation is very different between teams. The content of a low-power SoC may vary from one Always-On block driving the rest of the SoC as an extinction island, up to the first implementation of a closed-loop system to perform adaptive voltage scaling.
The purpose of this paper is to give an overview of the possible power gains at the different steps of a SoC development, starting from the requirements, through the choice of the best partitioning of the SoC into power islands and its synoptic, down to the silicon measurements, with a specific focus on the RTL to GDSII integration flow.
Dolphin Integration will share traps and tricks, inputs and outputs, and types of models required at each step in the integration flow for a low-power design: how to implement retention power islands, how to secure the functionality at SoC level by a combined verification with Synopsys tools and other solutions.
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