System-on-Chip (SoC) integrators have to put in place appropriate verifications in order to guarantee performance of analog Virtual Components (ViCs), also called IP blocks, once integrated into the SoC.
Such performances may be affected by various kinds of noise and the most critical issue in integrating analog functions is then to assess potential noise sources, to control noise propagation channels through the SoC and to evaluate noise impact at the interface between the ViC and the rest of the SoC.
Due to exponential increase of SoC complexity, flat simulation at top level is not achievable with the appropriate level of accuracy. And the question becomes how to ensure high performances for analog functions taking into account their environment within the SoC?
Thus innovative simulation methods and models have been developed and qualified on silicon to allow SoC Integrators performing noise simulation of their SoC and then assessing the real performance of embedded analog ViCs at SoC level…