Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824, June 2010
G. Depeyrot, F. Poullet and B. Dumas
Keywords: Verilog-A, compact model, SPICE
Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and IEEE 1364.1-2002), the Verilog-AMS hardware description language includes extensions dedicated to compact modeling, as a superset, but does not define a subset reserved for compact modeling. This lack of specification combined with some SPICE related specificities, such as the distinction between models and instances, are both responsible for the speed and memory consumption differences measured between Verilog-A compact models running in Verilog-A simulators and the same Verilog-A compact models running in SPICE simulators after conversion of the Verilog-A models into compiled SPICE models. That is the reason why, after presenting these differences, this paper presents recommendations for developers of Verilog-A compact models who want to optimize their models for SPICE-like simulators and to facilitate the integration of said models into different simulators.
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