Relying on 30 years of experience in SoC design, Dolphin Integration has developped all the IP contributors for an ultra-low-power SoC, in partnership with TSMC, particularly relevant for IoT applications.
Extreme reduction of power consumption of a whole SoC requires a power domain architecture, a truly complex task for SoC integrators. To reach this objective, more than usual semiconductor IPs is necessary to enable the performance needed for SoC differentiation on competitive markets.
In order to help fabless suppliers reach extreme optimization and win market share, the Dolphin way is to fill in the missing elements of know-how and components of IP.
The missing elements contributed by Dolphin Integration:
- ultra low power libraries:
- low dynamic power SRAM memories, low leakage standard cell libraries for AON working at 0.55 V, and low dynamic power standard cell library, low power microcontrollers, power reducing cache controller etc.
- a set of control IPs: to manage easily the mode transitions named Maestro, and an innovative power gating solution (CLICK).
- Innovative IDE and EDA solutions to optimize the power consumption during software development and ensure SoC functionality
- The integration flow complements followed a low power methodology experimented and demonstrated in actual SoC implementations, thanks to our SoC integration expertise
Contact nelly.albertini@dolphin.fr for further information on such IP contributions: components, EDA solution and know how, to increase the low power value of your projects.
