The growing demand for BCD technology aims at facilitating the integration of logic and analog with relatively high-voltage features on the same SoC for such volume applications where 5 V is due to the USB standard, enabling embedded power regulators with chargers, as well as higher sound power of Audio DACs. Moving to the 130 nm process helps further reduce both cost of silicon area and of BoM for devices on the printed circuit board.
The need for programmable power management networks with embedded MCUs benefits from Dolphin Integration’s portfolio of densest ROM generators, with patented bit-cell optimizations. The company today announces the availability of the silicon proven CASSIOPEIA generator for metal programmable ROM, at the TSMC 130 BCD 5V process.
“We are happy to announce that the ROM CASSIOPEIA generator is now available free of license fees, for all TSMC 130 nm BCD users. This product is tuned to meet the requirements of SoCs embedding Power Management Networks”, said Elsa BERNARD-MOULIN, Marketing Manager at Dolphin Integration.
The ROM CASSIOPEIA significantly reduces power consumption
- A 50% gain in consumption power has been proven compared to usual ROM from contenders.
- CASSIOPEIA optionally features the capability to operate at low voltage, down to 1.2 V +/- 10%: 40% power reduction compared to nominal voltage operation at 1.5 V +/-10%.
Benchmark results have also demonstrated that this Via 1 programmable ROM achieves an average of 20% gain in density compared to other solutions.
The ROM CASSIOPEIA has now passed the pre-silicon assessment criteria (level 1) of TSMC’s stringent IP9000 qualification program. The product is already implemented in many mass production designs in other 130 nm process variants.
Dolphin Integration offers a complete panoply for the TSMC 130 nm BCD process including a 6-Track standard cell library but also RAM and ROM memory generators.
Please click here to request a free access to the FE generator for evaluation purpose or to the BE generator for integration.