Dolphin Integration announces its participation to the TSMC Open Innovation Platform® (OIP) Forum at the Santa Clara Convention Center, CA.
During the event Gilles Depeyrot, CEO of Dolphin Integration, will present a breakthrough low-power design methodology associated with a set of standardized Virtual Components of Silicon IP enabling to optimize low power networks in a SoC as well as associated modeling and simulation solutions.
« Our objective is to provide standardized building blocks for power, control and clock networks to simplify SoC integration by our customers while optimizing the overall power consumption. » stated Gilles Depeyrot.
As reducing power consumption is a real challenge, the presentation will deal with How to avoid blindness about power consumption during low-power SoC design?
- Selection of specific IPs for the always-on domain
- Implementation and control of power domains
- Optimization of a low power SoC during software development
- Construction of noise resilient subsystems
Attendees are also welcome to visit Dolphin Integration’s booth #312 in order to go further and discover the Silicon IP product portfolio.