Dolphin Integration provides its customers with a complete set of Foundation IPs in TSMC 55 nm uLP and uLP eFlash processes; these are specifically designed to help reduce the SoC power consumption during sleep and active modes.
Lowering the SoC power consumption to support battery-powered devices has always been a challenge for designers. Dolphin Integration’s foundry-sponsored offering of Foundation IPs provide SoC designers with unprecedented capabilities: an instance of 8kx32 of the SpRAM RHEA features a dynamic power consumption as low as 23.14 μA/MHz at 0.9 V, whilst supporting dual rails to enable data retention at a voltage as low as 0.6 V, with minimal leakage.
The foundry-sponsored Foundation IPs include standard-cell libraries (6T and 9T), a power management kit as well as a complete set of RAM and ROM generators, Sp/Dp/1pRF/2pRF. Designers leveraging low-power design architectures, such as powergating, dual rail, operations at low voltage, are able to reduce their SoC power consumption by up to 70 % compared to LP processes. Furthermore, the ready-to-use characterizations operating at voltages ranging between 0.9 V and 1.2 V allow to reach the targeted SoC frequency with the lowest power consumption. Evaluation kits are provided on request to assess quickly and objectively the achievable performances.
Such standard cell and memory libraries are provided with a complete set of deliverables to achieve the best Time-To-Market. Furthermore, having passed the TSMC IP 9000 Level 4 qualification in both 55 nm uLP and 55 nm uLPeF, these foundry-sponsored Foundation IPs can be used safely. Other 55 nm processes, such as 55 nm LP, LP eF and 55 nm HV, are also supported.
More than 15 companies currently rely on our offering at TSMC 55 nm to successfully design their SoCs. The most complete catalog of silicon IPs in 55 nm uLP/uLPeF is available on request to design cost-effective and ultra-low power SoCs. For more information, please check out:
Discover catalog in TSMC 55 nm uLP and uLP eFlash
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