Eric Esteve, from SemiWiki.com, highlights the key elements of the recipe for an SoC to consume less than 0.5 µA in sleep mode. >> Read the article on SemiWiki.com website… The video of this webinar is now available on our private space, MyDolphin. Request an access if you do not have one yet.
Tom Simon, Technology Analyst at SemiWiki.com, shares his view on the importance to optimize the power consumption of SoCs in their sleep modes and on the worth of silicon IP solutions presented by Dolphin Integration during TSMC Symposium held in Santa-Clara in mid-March. Read the article on SemiWiki.com website…
Dolphin Integration will hold a live webinar on November 15, 9:00 AM PST or November 22, 10:00 AM GMT. This webinar targets the SoC designers wanting to learn how to quickly implement ultra-low power (uLP) techniques, using proven recipes. Read this press announcement on SemiWiki.com… Access to the webinar recording
High-level synthesis for event-based systems Second International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2016), Jun 2016, Krakow, Poland. This paper envisions a design flow for empowering designers in the fast development of low-power event-driven processing chains. This flow takes advantage of level-crossing sampling schemes and asynchronous circuitry. Event-driven paradigm allows better-than-worst-case performance …
Silvaco today announced that Dolphin Integration, a leading provider of power and density optimized memory silicon IP, has selected Silvaco Variation Manager TM, coupled with its mixed-signal simulator SMASH™ to perform critical variability analysis and reliability qualification on SRAM memories designed using advanced process technologies. Read this press announcement on Silvaco website… I want to …
Mixed simulator SMASH™ coupled with SILVACO Variation Manager Read More »
The LISA project will develop dual-interface chips, designed for secure RF (radio-frequency) applications such as banking, ID, transport or connected objects, using innovative wireless technology offering substantial costs reduction during the card manufacturing process. StarChip is the project leader of a collaborative task force, which brings together SPS, Dolphin Integration, Morpho, and 2 public research …
Associated news: Aug. 21 – Build an ultra low power SoC thanks to implementation-ready solutions Aug. 10 – Dolphin Integration and TSMC collaborate on Low-Power IoT Subsystem Design Get more information on this offering
Five actors emerge in TSMC’s Ecosystem for serving best the nascent IoT market. Read the full article…
Dolphin Integration launched a new 32-bit microcontroller, RISC-351 Zephyr, targeting low-power SoCs for IoT-like competitive markets taking into consideration three angles for optimization of power consumption: architectural, memory and software. Read the full article on SemiWiki.com >
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