Foundation physical IP for Energy Efficient SoC

We provide a broad and consistent range of embedded memories, power gating solutions and Logic libraries for designers seeking low power with no trade-off on silicon area.

We thoroughly validate our foundation IP portfolio, combining foundry qualification standards and our own stringent correlation process – the ‘Virtual Fab Process’ – to help designers accelerate their SoC development, enabling easy integration and high fabrication yield, from 180 nm down to the most advanced nodes.

Our Foundation IPs embed power management features (multi-Vt/multi-channel libraries, multi-VDD characterization, integrated power-switches, source-biasing…) which allow designers to explore the SoC architecture. Optimal configurations can be generated to meet the application’s Performance, Power and Area constraints. We also complement our offering to reach best-in-class Energy Efficient SoC by serving Always-On power-domains with a dedicated offer, optimized to achieve the ultra-low-power requirements of battery-operated devices in sleep mode.

Embedded Memories

Ultra-low power, high density single rail SRAM, Register files and ROM.

Our memories support multiple power modes for greatest operational flexibility between performance, power savings and wake-up time.

Power Gating solutions

CLICK power switch, with its fine-grain in rush current management, achieves the lowest leakage current automatically, by selecting max values of IR Drop, island size and total capacitance when defining the ring of power switches.

Logic Libraries

Standard cell libraries optimized for supporting ultra low power applications such as battery powered IoT or wearable devices.

We offer two architectures: uHD for low dynamic power and BiV for low leakage.
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