Foundation physical IP for Energy Efficient SoC

We provide a broad and consistent range of embedded memories, power gating solutions and Logic libraries for designers seeking low power with no trade-off on silicon area.

We thoroughly validate our foundation IP portfolio, combining foundry qualification standard and our internal stringent correlation process – the ‘Virtual Fab Process’ – to help designers accelerate their SoC development, enabling easy integration and high fabrication yield, from 180 nm down to most advanced nodes.

Our Foundation IP embed power management features (multi-Vt/multi-channel libraries, multi-VDD characterization, integrated power-switches, source-biasing…) allowing designers to explore SoC architectural universe among Performance, Area, and Power and generate their optimal configurations, meeting their specific application challenges. We also complement our offering to reach best-in-class Energy Efficient SoC by serving Always-On power-domains with a dedicated offer, optimized to achieve the ultra-low-power requirements of battery operated devices in sleep mode.

Embedded Memories

Ultra low power, high density single rail SRAM, Register file and ROM.

Our memories support multiple power modes for greatest operational flexibility between performance, power savings and wake-up time.

Power Gating solutions

CLICK power switch, with its fine grain in rush current management, allows achieving automatically the lowest leakage current, by selecting max values of IR Drop, island size and total capacitance when defining the ring of power switches.

Logic Libraries

Standard cell libraries optimized for supporting ultra low power applications such as battery powered IoT or wearable devices.

We offer two architectures: uHD for low dynamic power and BiV for low leakage.
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