connected and mobile world, IC designers are striving to save µA or even nA of
power consumption to extend battery usage without recharge. IoT applications
bring the need for LP to new heights involving the adoption of more complex SoC
architectures based on multiple power domains, which also require embedding the
whole power regulation network.
Such advanced SoC architectures significantly increase design complexity and may thus severely impact Time-to-Market and costs. As the power domains are dynamically switched on and off, the selection of the SoC architecture must be performed in full awareness of noise issues.
To watch this webinar, please register to our customer private space, MyDolphin >This webinar unveils a step-by-step design methodology to specify the power budget and master the design of ultra low-power and mixed signal SoCs. Based on a concrete example, it illustrates how to proceed for early budgeting of power consumption in consideration of noise issues in order to prevent excessive or insufficient design margins, which may be detrimental to silicon area and BoM cost.
The combination of this methodology with the use of SoC Fabric IPs, for building the clock, power and control networks, partakes in ensuring:
- the best TTM with the lowest risks,
- the optimization of SoC performances with the best trade-off between area, BoM cost, and power consumption.
Dolphin Design has proven the effectiveness of this structured design methodology ensuring IP compatibility with its Taishan demochip designed in partnership with TSMC at 55 nm uLP eF.
If the following questions come to your mind, you will certainly benefit from this transfer of know-how:
- How much reduction may I get from designing a SoC partitioned in multiple power domains?
- Which approach is the most efficient for budgeting power consumption of my SoC?
- Which new issues (noises…) should I be aware of to succeed the design of my ultra-low power SoC? What are the solutions to deal efficiently with these issues?
- How can I maintain reasonable Time-to-Market while adopting advanced design methodologies?
Who should attend?
architects and designers targeting to decrease their SoC power consumption, as
well as project leaders and design methodology managers needing to deploy a
low-power design flow for safer and faster tape-outs.
It provides insights into low-power architecture selection along with tricks & tips for ultra low-power SoC implementation
To watch this webinar, please register to our customer private space, MyDolphin >