The explosion of intelligent IoT devices and connected vehicles, supported by a fast-growing communication and processing infrastructure, is creating an exponential demand for energy. If we want to properly use our limited resources, energy saving must be considered as our main innovation focus.
When it comes to IC design, we can distinguish the two following approaches:
– More speed, same power: achieve more computing power with the same energy budget
– Same speed, less power: achieve same level of performances with a drastic power consumption reduction
System-on-Chip architects and designers are now playing in this new technical paradigm and have to adopt innovative technologies and methodologies to reach their SoC PPA targets.
The webinar will start with an overview of the multidimensional challenges faced by IC design teams to enable energy-efficient SoC for heterogenous product profiles.
Process selection is the first step to build an energy-efficient device. You will find out how FDSOI technology enable unique features such as body-biasing to reach the stringent power consumption target of battery-powered IoT devices while ensuring high performance and high reliability for more demanding markets such as automotive applications.
Then, you will discover how a turnkey, fully integrated on-chip solution can bring you unexpected PPA figures by enabling adaptive process, voltage, temperature and aging compensation, creating a wining combo with established low-power techniques such as DVFS.
The last part of the webinar will focus on the methodology required to enable a smooth and seamless adoption of an adaptive body-biasing solution. Our experts have worked on it and we will unveil their experience based on a concrete example.
Who should attend?
SoC architects and designers involved in energy-efficient SoC designs. Project leaders, design managers and IC design directors needing to deploy new solutions to improve their SoC energy efficiency
Prerequisites: it is better to have basics on low-power architectures
