Dolphin Integration of Meylan, France and Dolphin Delegation, their subsidiary dedicated to Design Services, announce at SAME 2003 starting on October 8, the opening of their System-on-Chip (SoC) Integration Center in the Telecom Valley.
SoC designers daily face the importance of hardware/software co-development, and the growing hurdles of SoC Verification, while current trends show that 70% of Systems-on-Chip are expected to be mixed-signal in 2007.
Dolphin’s MEDAL approach to contribute “Missing EDA Links” makes feasible cosimulation of separately available simulators: the link between mixed signal simulation and In-Circuit Emulation was missing! For verifying a whole SoC, typically mixed signal for Telecom applications, as well as its application software, a new design flow is made feasible:
starting from the C-compiler and the Instruction Set Simulator, whatever the processor, the linking by SUCCESS™ with the models of the interconnected memory, logic and analog peripherals, especially Codecs, enables early virtual exercising of both the SoC interconnect Testbenches and embedded applications.
Thanks to its 18 years of accrued expertise in both analog and logic design along with the development of appropriate EDA solutions, the DOLPHIN Group, the Mixed Signal SoC Enabler, promotes SUCCESS™: this Virtual In-Circuit Emulator (ICE), enabled for mixed-signal SoCs by the celebrated SMASH simulator, can be used at three stages of the design flow: to validate the choice of architecture, later to check the hardware configuration, and to fine tune the embedded application program.
This exclusive know-how, shared with Dolphin Delegation’s consultants and customers through internal and external training programs, is enhancing their contribution to the Telecom Valley with the opening of Dolphin Delegation SoC Integration Center
About the DOLPHIN Group
Provider of Logic, Analog and Memory Virtual Components with a technological focus on low power-consumption and a market emphasis in audio-processing, the Group now innovates with its specialty in hierarchical SoC design: engineers thereby get a unique exposure to state-of-the-art solutions based on “Hierarchical Link Editor” SoC HLE and “Virtual Socket Editor” SoC GDS as well as multi-level simulator SMASH to enable Virtual Testbenches, Verification Components and Virtual Instrumentation!
The corporate charter is to trigger productivity improvements for helping customers meet the growing challenges of Time-To-Market with a quality control process leading reliably to success on first pass.
All CMOS processes – bulk or SOI – are targeted from 0.6 µm down to 90 nm, with a safe and powerful technique for multi-foundry retargeting.
Design and support services range from turnkey development to delegation of consulting engineers for customers wanting efficient insertion of virtual components into their designs, and delivery of unique solutions for embedded software codesign…