With the growth of ultra-low power applications for the Internet of Things, users at TSMC 55 nm uLP could count on Dolphin Integration to bring a complete offering.
The foundry sponsored panoply at TSMC 55 nm uLP includes: single port RAM, one port register file, two port register file, dual port RAM, ROM, 6-track and 9-track standard cell libraries with Island Construction Kit (ICK).
But a low-power SoC needs the complete platter of a “low power panoply” (LoPan) with extremely low voltage (eLV) standard cell library SESAME HD-eLV for always on blocks, ultra high density standard cell library SESAME uHD with island construction kit SESAME CLICK for other power domains and low power Dual Output Regulator DOR-eSR-qLR enabling dynamic mode switching of power islands.
At TSMC 55 nm uLP, two different packages LOPAN-eLV and LOPAN-DOR guarantee you to find the solution closest to your needs with or without power regulators:
TSMC 55 nm uLP
|SESAME HD-eLV for always on blocks||LOPAN-eLV
low power Dual Output Regulator DOR-eSR-qLR
|SESAME uHD with island construction kit SESAME CLICK for other power domains|
Key benefits of LOPAN offering:
- Extra low power consumption in your always on block thanks to SESAME HD-eLV enabling functionality at the minimum data retention voltage of uHD (0.5 V min) for lowering both dynamic and leakage power
- SESAME uHD (pulsed latches) reducing for most logic blocks power by up to 30 % while saving up to 15 % area
- Safe and easy minimization of the flow with “FAIRY” (innovative alternative to daisy chaining) thanks to Dolphin Integration island construction kit SESAME CLICK
- SpRAM RHEA designed with partitioned array to reach ultra low power consumption at 1.2 V +/-10% and 0.9 V +/-10%
- The Reusable Power Kit Library (RPKL) for building voltage regulators to ensure the lowest power consumption of SoCs allowing mode switchings