How to define a robust and power-optimized power management architectureIP SoC 2012, Grenoble, FranceS.Genevey
Dec 05, 2012
How to define a robust and power-optimized power management architectureIP SoC 2012, Grenoble, FranceS.Genevey
Abstract
Context: SoCs complexity increase with constraint of power consumption reduction.
Solution to reduce power consumption: SoC partitioning in power and voltage islets with several states of activity.
Issue to solve: properly select the power management network (PMNet) including power regulators, external and internal capacitors to sustain the voltage drops caused by mode transitions.
Traps:
PMNet not sized appropriately, the SoC may not operate properly.
PMNet over-designed, silicon area wasted or Bill-of-Material increased.
