Abstract
- Context: SoCs complexity increase with constraint of power consumption reduction.
- Solution to reduce power consumption: SoC partitioning in power and voltage islets with several states of activity.
- Issue to solve: properly select the power management network (PMNet) including power regulators, external and internal capacitors to sustain the voltage drops caused by mode transitions.
- Traps:
- PMNet not sized appropriately, the SoC may not operate properly.
- PMNet over-designed, silicon area wasted or Bill-of-Material increased.
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