Dolphin Integration is releasing SESAME CLICK, a kit of cells enabling the construction and integration of islets. Its low power cells optimized for TSMC 65 nm and 55 nm processes is enriched with a patented Transition Ramp Cell for an easy and safe construction of low energy circuits.
SESAME CLICK minimizes power consumption through:
- Support of logic blocks with multiple voltages, through level shifters.
- Support of power gating with or without retention of data, through always-on cells, retention spinner cells, isolation cells, filler cells, corner cells and of course power switches.
The 65/55 nm CLICK, coupled with the intrinsic density advantages of 6-Track standard cell library, SESAME uHD-BTF, enables SoC designers to reach whatever leakage reduction they aim at!
SESAME CLICK leaves far behind the first generation of cells for power management.
For reaching top performances, Dolphin’s CLICK features
- « Retention spinner cells » with pulsed latches replacing retention flip-flops with balloon latches for up to a 4-times gain in density!
- Scripts for automatic computation of the optimal number of switches required for islet construction
- Low voltage retention capability down to 0.77 V at 65/55 nm.
SESAME CLICK is not only a power and cost effective solution, but also a solution guaranteeing a straightforward integration of islets, to solve the key issues of in-rush current, of islet integration and of switch placement.
Advanced features for a successful integration of power and voltage islets
- The patent-pending Transition Ramp Cell (TRC) handles an automated limitation of the inrush current caused by mode transitions
- The ring style for switch placement enables easy integration of hard macros
- CLICK is provided together with a script ensuring the automated insertion of the ring and the sizing of the switches
- The associated transfer of know-how in modeling and simulation helps guiding the user to size any power regulator with its islet and conversely.
For more information, feel free to download the Presentation Sheet.
For performing fast your own benchmark of this silicon IP on your design, just click here and request an access to the evaluation kit.
Our Integration and Application Engineers provide support to define the most suited combination of silicon IPs and the best SoC architecture for your project.
Please contact firstname.lastname@example.org for more information.