Dolphin Integration demonstrates the excellence of its expertise in design and integration services through the development of a new circuit showing performances never reached. This development was performed in the frame of the preparation of the “Loft mission”, scientific satellite of X-ray detection, in close collaboration with IRAP (Institut de Recherche en Astrophysique et Planétologie) laboratory and CNES (Centre National d’Etudes Spatiales).
This circuit aims to interface with a SDD sensor (Silicon Drift Detector). It embeds complex and low noise analogic blocs like a pre-amplifier, a shaper and a peak & hold. It offers the best noise and temperature linearity performances on the market: the noise was measured at 21.6 electrons at 25°C, which is twice better than most of this type of circuits on this market!
These performances were achieved while respecting the low power consumption constraint with a result under 320 µA at 1.8 V.
The silicon measurements are fitting perfectly the initial specification of the circuit and the simulations. They were realized on prototypes using a 180 nm technology, at temperatures between -50°C and +25°C.
“IRAP had the technical responsibility of the R&D contract signed between Dolphin Integration and the CNES for the study of this ASIC: functionality and performance specification and development follow-up. The low-noise and low-power consumption constraints were huge and the development schedule was very short (5 months). Thanks to a close collaboration with the development team of Dolphin and its efficiency, the tape-out date was respected. The noise and power consumption specifications are reached.
This is a good collaboration example between a research laboratory, the CNES and the industry, which results in a high performance product. The next step of this collaboration will target an ASIC close to the instrument needs of LOFT” declared Alain Cros, ASIC project leader for the LOFT mission.
Thanks to this success, the ASIC designers of Dolphin Integration demonstrate their knowledge at the state-of-the-art and strengthen their leadership in mixed signal ASIC.
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