Discover CHAMELEON, a revolutionary event-based MCU subsystem

Grenoble,
France – June 12^th, 2020

The MCU market is facing a profound revolution to address the challenges of data processing for edge computing IoT applications. Traditional MCU subsystem architectures have too many limitations to keep pace with the edge and very edge computing market requirements for energy efficiency. New solutions have to be implemented.

We have unlocked these limitations by implementing a disruptive architecture based on a CPU-less and event-based data management system. This new subsystem architecture, called CHAMELEON, is compatible with any CPU, DSP and NPU through a standard AMBA interface.

CHAMELEON benefits are manifold:

Capability to process and store data to SRAM while the CPU remains in deep sleep mode

High bandwidth access to SRAM through innovative low latency interconnect

Tiny Machine Learning (ML) accelerator with 32 MAC/cycle

Active power consumption below 15 µA/MHz in 22FDX

CHAMELEON flexibility allows front-end designers to accelerate their design cycle, using a full plug and play approach along with all necessary drivers and RTL configuration tools.
CHAMELEON comes pre-verified and silicon proven on various process nodes. It is fully interoperable with our SPIDER power management platform to achieve the highest possible level of energy efficiency.

Choose the innovative architecture. Do more, with less energy.

Adopt CHAMELEON.

—– NEW PRODUCT —–

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