Nov 27, 2017

Breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA

The BCD process technology has been around since the mid-eighties, but there has more recently been phenomenal interest and growth in BCD technology. This has been driven by the growing need in Power Management IC (PMICs), motor-control, power audio and many other applications targeting the consumer, industrial or automotive markets. The need for more intelligence embedded in these integrated circuits has led to the integration of MCUs and consequently of RAMs, with growing requirements for larger capacity.

Relying on robust, dense and low-power RAMs is pivotal for Fabless companies; the appraised single-port RAM RHEA compiler combines all three of these characteristics. Users of the TSMC 180 nm BCD Gen 2 process now benefit from the most competitive RAM. Thanks to its innovative architecture, the density of RAMs has improved by up to 30% and dynamic power consumption savings can reach up to 50%. Furthermore, the single-port RAM RHEA compiler supports multiple power saving modes, thus reducing static power consumption by up to 8 times in minimum data retention mode, as low as 1.0 V, compared to stand-by mode.

A SpRAM RHEA instance of 2kx32 is as dense as 0,342 mm2 and features a dynamic power consumption as low as 65,27 uA/MHz, with a leakage current reduced down to 1,6 uA. SoC designers targeting the TSMC 180 nm BCD Gen 2 process now benefit from a ready-to-use compiler to instantiate RAMs between 256 bits and 328 kbits. Multiple form factors are supported to ease SoC integration. The memory compiler provides all views needed for a fast and smooth SoC integration including for BIST support.

“This new RAM compiler for the TSMC 180 nm BCD Gen 2 process relies on our robust RHEA architecture,” says Frederic POULLET, Business Operations Manager for memories at Dolphin Integration. “The SpRAM RHEA has benefited from our stringent qualification process and is silicon proven in numerous processes down to 55 nm, in various variants such as uLP, uLPeF, LP, LP eF and HV. The BCD process technology is a perfect example of the relentless innovation that drives the semiconductor industry in terms of application, design and process technology. Driven by markets that did not exist some years ago and the increasing interest from SoC designers for its impact on power loss, cost and board space, the demand for the TSMC 180 nm BCD Gen 2 process has exploded in recent times. We are very excited to contribute to this trend.”


Discover our SpRAM RHEA in BCD Gen 2 process

To streamline the evaluation process of SoC designers, the SpRAM RHEA compiler for TSMC 180 nm BCD Gen 2 process is now available on our MyDolphin secure space.It allows you to test any memory configuration and to generate the full set of front-end views including .LEF files.

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