Automated on-the-fly verification of designs using detector-based methodology
Dirk Dammers, Wei Guo, Frédéric Masson, Lars M. Voßkämper
Mixed-signal simulation of systems, i.e. analog & digital electronics with attached peripherals, such as sensors and actuators, already has an essential place in today’s design process. While the verification of the digital parts, mostly implemented in Verilog and VHDL, has gained a speed and quality increase through the use of Assertion-Based Verification (ABV) with Property Specification Language (PSL) and System Verilog Assertions (SVA), analog verification suffers from not being supported by these assertion description languages. To speed up and secure the verification of the analog parts (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
Based on the assertions approach, this paper presents an innovative methodology for the verification of analog and mixed-signal circuits which embeds detectors at each step of the hierarchical verification process to increase Quality Control and reduce Time to Market. This paper illustrates the approach with the input range and phase shift verification of the Analog Front-End (AFE) of an Energy Meter. It does not discuss strategies to verify the complete functionality of the design.
Index Terms— mixed-signal design verification, design debug, detectors, specification, assertion.
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