Introduction
System integrators often encounter problems on application boards too late in the design cycle, when bringing together Virtual Components (ViCs of silicon IPs) into a system. Some ViC performances may be degraded at higher levels (SoC and PCB), and thus the final system does not perform as well as expected. In other words, assembling high-performance ViCs together does not guarantee high-performance SoCs or systems when fundamental integration aspects are not addressed or key issues are violated during the integration process.
In order to maintain the performance of each ViC at higher integration levels, and thus guarantee the functionality of the entire system, one must understand how much the overall system performance is sensitive to interactions between the components, including key functions such as clock, power regulation, voltage reference… and propagation of degradations through these networks must be taken into account. The impact of the Power, Reference, Clock & Detectors Network (PRC&DN) design must be assessed and addressed at the system level in order to maintain the performances of the system functions.
In order to reduce the risks when integrating several ViCs, the SuperViC approach, which consists in providing pre-assembled ViCs to facilitate the integration at SoC level, will be described. We will demonstrate the benefits of integrating a SuperViC, in comparison with the integration of the individual ViCs, through an example of power supply noise causing performance degradation. At SoC level and at application board levels, the trickiest task is to design the PRC&DN correctly to maintain the performance of the ViC or SuperViC together with its application schematics. Finally, an innovative offering, which combines SuperViC, Application Hardware Modeling (AHM) and Custom Training Package, is presented…
