With the growing chip complexity observed in many market segments, in addition to a need for longer battery life, SoC design teams are forced to adopt advanced power management techniques to improve the energy-efficiency of their devices. Recent process nodes offer a high level of SoC integration with RF connectivity, logic MCU, non-volatile memory, AI/ML processor and analog blocks on the same die, so system and power architects now have to deal with:
- Fast wake-up times to ensure instant-on operation from sleep and stand-by modes
- Control of multiple voltages on the same die to supply MCU/logic, RF, analog and SRAM domains
- Fine-grain control of power and clock gating to instantaneously switch-on / switch-off domains
- Increasing number of power modes for maximum flexibility at application-level
- Fast transitions during power mode changes to minimize energy consumption