MAESTRO -
Speed-up your SoC design with a configurable Power Controller RTL IP
The need to control power

With the growing chip complexity observed in many market segments, in addition to a need for longer battery life, SoC design teams are forced to adopt advanced power management techniques to improve the energy-efficiency of their devices. Recent process nodes offer a high level of SoC integration with RF connectivity, logic MCU, non-volatile memory, AI/ML processor and analog blocks on the same die, so system and power architects now have to deal with:

  • Fast wake-up times to ensure instant-on operation from sleep and stand-by modes
 
  • Control of multiple voltages on the same die to supply MCU/logic, RF, analog and SRAM domains
 
  • Fine-grain control of power and clock gating to instantaneously switch-on / switch-off domains
 
  • Increasing number of power modes for maximum flexibility at application-level
 
  • Fast transitions during power mode changes to minimize energy consumption

 

Designing a custom logic to control the devices involved in power management requires an in-depth expertise and drastically increases the design and verification cycle time.

We created MAESTRO, a unique Power Controller RTL IP which is accompanied by PowerStudio compiler to speed-up the design of a highly scalable power controller that features breakthrough capabilities compared to traditional HW or SW PMU design methodologies.

 

Benefits from the power of MAESTRO

performances

PERFORMANCES

  • Dual operation mode: CPU-less HW mode & SW mode
  • Low latency control of power devices involved in managing power – Fast & autonomous wake-up with no need for external clock source
  • Support of advanced low-power design techniques (DVFS,…)
Chrono

REDUCED TTM & COST

  • Near-zero design iteration cost: reduced cycle time compared to conventional PMU design flow
  • PowerStudio GUI Compiler: fast path from architecture to integration & quick iterations
  • Sustainable & scalable: same solution for heterogenous IC, scalable to any SoC complexity
sceured chip

REDUCED RISKS

  • Fully autonomous boot-up sequence
  • Automated test-bench generation for faster validation
  • Open to 3rd party IP integration with P-channel interfaceS
MAESTRO features
  • Dual operation mode
    • CPU-less HW operation mode for low-power and low latency control of power devices
    • Flexible SW operation mode with a standard 32-bit APB interface that enables on-the-fly execution of SW-based power sequences
 
  • Embedded sequencer for autonomous control of power mode transitions, including boot-up and wake-up sequences where CPU is off.
 
  • Event-based architecture to trigger any power sequence (up to 16 pre-programmed HW events)
 
  • Built-in always-ready 10 MHz oscillator to enable fast wake-up when RTC clocks are shutdown
 
  • Fine-grain control of power devices (regulators, clock generators) with standard p-channel interface, enabling smooth support of both IP from Dolphin Design or 3rd party provider

POWERSTUDIO Compiler: Fast path from specifications to integration

MAESTRO is augmented with PowerStudio compiler to enable a faster path from architecture to integration, featuring:

  • Power State Table and Power Mode Changes GUI for fast configuration: design in a single day, iterate in a single hour
 
  • MAESTRO gate count & transition time calculator
 
  • Automated generation of MAESTRO RTL configuration
 
  • Automated generation of UPF test-bench for PMU in-context verification

MAESTRO is part of SPIDER, Power Management platform

"If you are short in time or if you lack proper resources to go through the sophistication of very complex power architecture, you can stick to something that is relatively simple and still benefit from this highly automated flow."
E. Flamand, CTO - GreenWaves Technologies

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