Discover our SRAM ERS
SRAM with intelligent power gating
Embedded Memory Compilers
High density / Low power embedded memory compilers
For more than 25 years, Dolphin Design has continuously enriched its embedded memory IP portfolio to provide high-quality ROM, SRAM and Register File Memory-compilers, available from 180nm down to 28nm in various foundries and process variants.
Dolphin Design’s memory-compilers are optimized for high-density and low-power while providing a great flexibility and a fine granularity providing the designers with the capacity to find the optimal trade-off between performance, power and area.
Our embedded memories are endowed with multiple power saving features (various power saving modes, embedded power switches with in-rush current limiter, source-biasing, multi-VT periphery…) to minimize both static and dynamic power consumption. Moreover, options for overdrive/low-voltage PVTs and for dual-power rail makes possible to support dynamic voltage and frequency scaling (DVFS).
Dolphin Design’s memory-compilers are extensively silicon proven, and designed to provide highest yield thanks to our thorough validation methods.
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SRAM and Register Files
“Dolphin Design’s SRAM and register file compilers have been designed to achieve minimum area and power while meeting aggressive timing requirements.
Single port (SP), dual port (DP) or 2-port memory (2P) compilers are available, depending on the technology node.
These best-in-class memory compilers rely on a smart architecture to provide the optimal solution to various design needs in terms of performance, power and area combinations.”
Multiple Power Management Modes
Multiple low power modes are available, enabling power-optimized SoC design with the flexibility to select the best compromise between power saving and response time. Retention and shut-down modes provide a progressive reduction of leakage power compared to stand-by mode.
Several options to address various needs
To reach low power and exploit all the benefit the technology can offer, Dolphin Design, propose a large choice of options for SRAM that can be combined at ease. (Move on GIF to access on details)
High Density – Retention Ready
Embedded Retention & Shut-down switches
Retention Ready & Source Biasing
ROM memory compilers
From the inception of the company, Dolphin Design has acquired a strong know-how in Via ROM design that has resulted in multi-patented ROM compilers. Thanks to its unique bit-cell and its power aware architecture, Dolphin Design’s Via ROM represents the best combination of high density and low power available on the market.
A compact via programmable ROM array (with a single programming layer) featuring high-speed read enabled by reduced stray capacitance. sROMet enables reduced area with lower dynamic consumption compared to traditional via ROM.
Its multi-bit data per ROM cell, featuring ultra-high-density, targets high capacity ROM up to 8 Mb. This patented architecture offers huge area reduction while keeping a reduced dynamic consumption compared to traditional ROM.
Key Benefits of all our embedded memory compilers
- Multi-Vt periphery for combining performance with low power
- Multiple power management modes with embedded power gating
- Multi-VDD characterization (overdrive/low voltage support)
- Memory optimized over multiple sub-spaces based on MUX and segment combinations.
- Multiple configurations available enabling to find the optimal PPA trade-off
- Data range flexibility allows easy addition of bits for ECC purpose.
- Address range flexibility allows easy addition of single row for supporting redundancy
Wide and versatile offering
- Available in many different foundries (TSMC, SMIC, GLOBALFOUNDRIES, UMC, HHgrace) and process nodes
- Memory compilers natively designed for easy migration to another process variant or to another foundry
- Millions of wafers manufactured with Dolphin Design's memories
- Repeatedly selected by TSMC for "sponsored library program"
- Stringent quality checks leading to right-on-first-pass design
- Electrically, physically and EDA-view aligned with standard-cell library and voltage regulators
- Supports major EDA tool flows (Cadence, Synopsys, Mentor...)
- Custom PVT support
- Fast and efficient technical support
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Memory Test and Repair features
Test and debug
- Proprietary Memory BIST
- Debug and diagnostic option enables SoC integrators to identify errors and to specify whether these errors are due to the process or due to the design. This option helps to diagnose yield loss and to define the appropriate corrective actions.
- Fill/check option enables to fill the whole memory with a given pattern and to check that each write & read operation is successful.
- Full support of Tessent Memory BIST (from Mentor)
- Key for supporting SoCs with a large number of memory instances
- Fully automated & integrated BIST insertion
- Self Repairable RAM (starting from 28nm) supporting various redundancy schemes.
- Easy control of Area, Speed and Yield trade-off