The solution to reduce by up to 99.9% the leakage of your SoC implementing safely power gating
The fastest & safest solution for power gating
Universal power gating kit to implement power domains in a single pass
Save energy partitioning your SoC into power islands whatever their content, and implement them in a single-pass using our CLICK fabric IP, with no risk of excessive in-rush current or wake-up time thanks to its patented Transition Ramp Cell.
Any Standard Cell Library
- Dolphin Design library: SESAME 9T, SESAME HD (6T) or SESAME uHD (6T)
- Foundry High Speed library
Its Power Management Cells
- Dolphin Integration SESAME ICK (Islands Construction Kit)
- Foundry Coarse grain cells (Power Management Kit or Power Optimization Kit)
- Level shifters
- Isolation level shifters
- Isolation cells
- Always-on buffers and inverters
- Retention cells
- Power switches (grid style)
- Power switches (ring style)
- Ring cells
- Transition Ramp Controller (TRC)
- Automated implementation
- Ring creation scripts for Cadence and Synopsys P&R solutions
Our customers talk about the CLICK
Interview of Eric Flamand, CTO of Greenwaves Technologies, explaining how they adopted our CLICK in their first “IoT Processor”.
Operating the whole design or some subsystems at a lower voltage enables to save dynamic power, while leakage power can be drastically reduced by shutting down unused parts of the design
Incremental solutions to save power consumption
Implementing power domains for shut-down with one regulator for each voltage domain, at the cost of BoM and silicon area. Power gating is then easily handled by turning on or off the regulator, at the expense of significant wake-up time.
CLICK, the universal power gating solution
Managing power gating with the CLICK enables:
- Creating power domain* whatever their contents (standard cell logic and/or hard-macro),
- Handling safely and automatically the trade-off between wake-up time and in-rush current, up to register programming
- Avoiding oversized margins and design iterations thanks to abacus dimensioning and register programming)
- Enabling designer to re-size the power gating implementation to reach a better IR-Drop or a lower leakage without re-routing the block thanks to ring style
* using our script with Cadence or Synopsys Place and Route solutions
Implementing power domains for shut-down or retention, sharing a voltage regulator for several power domains, leading to saving both area and BoM cost while optimizing wake-up time. Power gating is then handled by turning on or off, locally, each power domain according to SoC activity modes.
…which can be used for any kind of power domain
Pure logic power domain
Composite power domain
Fitting power domain of any polygonal shape
CLICK can be applied to any power domain whatever its nature and origin, and provides a unifying power gating strategy for a complete low power SoC.
CLICK key benefits
Flexible in-rush current management
Automated limitation of in-rush current, enabling a « correct-by-construction » implementation thanks to patented TRC cell
Short wake-up latency (hundreds of ns)
Easy tuning (hard and soft programmable) of “wake-up latency vs in-rush current” trade-off, even after tape-out
Single power gating solution at SoC level Applicable to any hard macro supplied at core voltage Applicable to any digital logic block whatever the library provider (e.g. 12T sponsored library) Semi-automated and optimized power gating implementation thanks to dedicated scripts for sizing the switches, setting the maximum in-rush current allowed and creating the power switch ring around any polygonal voltage area.
Ring Style implementation
Does not create further routing issues in already congested design Enable quick update: no need to re-route the whole power gated block for exploring others strategies Allows optimization of the ring to reach a better IR-Drop without re-routing the block
Leakage power reduction
up to 99.9% leakage power saving in sleep modes Multiple VT, channel length and switch height for reaching the best trade-off IR Drop vs. Leakage
Benefit from an optimum package when combined with SESAME & our ICK add-on
Power Performance Area (PPA)
A multi-VT solution Allows low voltage operation and retention at very low voltage thanks to dedicated retention flops Reduce dynamic power by lowering voltage / splitting into multiple voltage domains Effective method for reducing leakage power in stand-by/sleep modes (by switching-off unused blocks) Area optimization thanks to the compatibility with our ultra High Density libraries (Sesame uHD) through dedicated retention spinner cells.
To shut down a block without losing register contents Fast method to get the block fully functional after wake up (resume operation in hundreds of ns) Capability to control always-on signals in power-gated blocks
Even better with our unique Fabric IPs...
Transition Ramp Controller for a safe power-up sequence
RC (Transition Ramp Controller) is a unique patented cell providing a self-regulated and reliable way to control the power-on sequence. During wake-up, the TRC controls the voltage level applied at the transistor gate to open progressively the power switches.
With TRC, in-rush current is automatically clamped to the maximum allowed (up to 8 power-on scenarios are dynamically programmable), providing the twofold advantage of avoiding IR drop issue and optimizing wake-up latency.
Our TRC enables:
- Automated limitation of in-rush current
- Max in-rush current value is dynamically controllable enabling a management of power-on sequence by software, after tape-out.
- Iterative and complex in-rush current analysis is replaced by a single verification
- Smart “control” of the trade-off between wake-up time and in-rush current
- Semi-automated power-on sequence including isolation and retention signal management
CLICK deliverables include scripts for an automatic power switch ring insertion and default TRC configuration.
The TRC of each power domain must be explicitly declared in Verilog. When used with Maestro, our unique solution to build the embedded power control network, TRC instantiation is automatically managed (transparent for the SoC designer).
SRAM with ERS option (Embedded Retention and Shutdown switches) embed a TRC to safely handle the wake up from retention and shut-down modes.