SoC performance metrics have changed, moving from pure performance objective up to performance efficiency with the lowest power consumption. This new metric, the Million operations per µWatt, is already crucial for IoT and mobile devices and is becoming key for a wide set of applications.
Designing an energy-efficient SoC is a challenge: it requires different specific skills all along the design flow, from the architectural step up to the physical implementation, in order to save every possible µA in both active and sleep mode.
Low-power design techniques have been deployed in mature processes, specifically related to the integration of the power regulation network. But migrating to advanced nodes comes up with new leakage challenges to meet stringent energy-efficient expectations from the market.
After a short description of the low-power techniques, this live webinar illustrates, through a concrete example, a methodological approach to identify the optimal power architecture. It also unveils new solutions to design cost-effectively and safely an energy efficient SoC using an advanced process.
To watch this webinar, please register to our customer private space, MyDolphin >
Webinar agenda
- Introduction: Vision on the constant need to improve energy efficiency with an overview of the low-power design technics to meet the market needs…
- Illustration, using a Bluetooth Low-Energy application, of a methodology to explore and compare objectively the worth of SoC power architectures. Analysis of the main contributors to the SoC power consumption for selecting the optimal power architecture…
- Focus on some technical challenges with advanced process nodes. Highlight on specific solutions to leverage unique FD-SOI process capabilities for minimizing SoC power consumption…
- Introduction of a complete and consistent Power Management IP platform. Breakthrough approach to help SoC architects and designers select and then implement easily and safely advanced low-power design techniques…
Who should attend?
SoC architects and designers involved in
energy-efficient SoC designs using advanced process nodes.
Project leaders and design methodology managers needing to deploy a low-power design flow for safer and faster tape-outs.
Prerequisites: it is better to have basics on low-power architectures, including power domains and power modes management. If needed, you can request an access to our last webinars dealing on “The proven recipe of an LP SoC” and “Recipe to consume less than 0.5 µA in sleep mode”.
To watch this webinar, please register to our customer private space, MyDolphin >
