Reducing Power Consumption of microcontroller sub-systems using a Cache Controller
Strong market requirements for decreasing the power consumption of embedded systems and increasing complexity of systems-on-chip require innovative solutions addressing such needs. In microcontrollers systems using memories like Flash, OTP, EPROM or EEPROM, the memories can consume a large part of the consumption of the whole system. Using a cache with such memories offers a double advantage. It first enables to increase speed performances by reducing memory latency and increasing throughput, which is the usual approach and, much more interesting if the cache is well parameterized and designed with appropriate features, it enables to significantly reduce the power consumption due to optimization of memory accesses.
For example, the power consumption of an embedded Flash in 180 nm process can be reduce up to 4 times and its average access time divided by 2 when using it with Dolphin I-Stratus-LP cache controller.
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